The present invention generally relates to computer system architecture, and more particularly, relates to a method and mechanism of automatic video buffer flipping and display sequence management in a computer system.
A typical computer system includes a processor subsystem of one or more microprocessors such as Intel(copyright) i386, i486, Celeron(trademark) or Pentium(copyright) processors, a memory subsystem, one or more chipsets provided to support different types of host processors for different platforms such as desktops, personal computers (PC), servers, workstations and mobile platforms, and to provide an interface with a plurality of input/output (I/O) devices including, for example, keyboards, input devices, disk controllers, and serial and parallel ports to printers, scanners and display devices. Chipsets may integrate a large amount of I/O bus interface circuitry and other circuitry onto only a few chips. Examples of such chipsets may include Intel(copyright) 430, 440 and 450 series chipsets, and more recently Intel(copyright) 810 and 8XX series chipsets. These chipsets may implement, for example, the I/O bus interface circuitry, direct memory access (DMA) controller, graphics controller, graphics memory controller, and other additional functionality such as graphics visual and texturing enhancements, data buffering, and integrated power management functions.
For graphics/multimedia applications, video data (i.e., audio and visual data) may be captured by one of these chipsets from a video source using general video capturing techniques, and concurrently displayed for viewing purposes. During active video or animation, a series of images may be displayed on a display monitor in sequential order. Video data may be sequentially stored in a series of buffers. Software is typically provided to drive video hardware specifically configured to sequentially store images in those buffers and xe2x80x9cflipxe2x80x9d display contents from one image to another. The flipping of display contents of images is activated through software interrupt service provided by an operating systems (OS) such as Microsoft Windows(trademark) 95/98, Windows NT(trademark) and Windows 2000(trademark). However, due to interrupt latency (delay) problem, the software-based method of flipping display contents of images can be inefficient and/or unreliable. Moreover, such a software-based method can also be cost-prohibitive and burdensome in terms of processor cycles required while increasing the likelihood of display quality problems in heavily loaded systems.
Accordingly, a need exists for a hardware-based automated solution to simultaneous video capture and display without the need for software intervention, that is, to relieve the software from the task of flipping display contents of images and increase the efficiency and performance of the simultaneous video capture and display functions while minimizing the likelihood of display quality problems in heavily loaded systems and the processor cycles required.
Accordingly, various embodiments of the present invention are directed to a hardware-based graphics controller for processing video data in a computer system. Such a graphics controller may include a video capture engine which captures fields of video data from a video source for storage in video buffers in sequential order, and generates video capture parameters from the video data for determining proper flipping operations of display contents of one image to another on a display monitor; and a video overlay engine coupled to the video capture engine, which determines proper flipping operations of display contents of one image to another from the video buffers and adjusts display settings of the display contents for a visual display on the display monitor based on the video capture parameters from the video capture engine.